% Device-to-processor Model
In order to implement circuit and architecture designs using emerging device-based technologies, we employ a device-circuit-architecture modeling framework to bridge the different design layers, as shown in Fig.~\ref{fig:modeling}. A lookup-table based TFET Verilog-A model has been widely used to accurately model the device performance in TFET prototype circuit demonstration and performance benchmarking. Here the device characteristics across a wide range of operation voltages can be directly obtained from full-band atomistic simulations~\cite{AvciIEDM2013} or from calibrated TCAD Sentaurus simulations~\cite{MichiganSRAM, VinayNanoarch2011}.  
The lookup-table based Verilog-A modeling also provides an efficient model development platform for alternative device designs based on different materials system, device architecture, scalability and operation range, but it also imposes limitations on circuit scale and complexity due to the increased CPU time in circuit simulation. 
Driven by the demands of practical circuit design and system analysis, compact SPICE models development for different TFETs have recently attracted lots of interest~\cite{ZhangIEDM2012}, aiming to achieve an accurate prediction of TFET operation. 

Based on the device models, various circuit designs using steep slope TFETs have been explored for ultra-low power digital and analog/RF applications~\cite{VinayNanoarch2011,TFETCNN,TrivediDAC2013, HuichuISLPED2013Rectifier} by taking advantage of the steep sub-threshold slope-induced energy efficiency benefits that these devices provide.  
Studies of TFET electrical noise modeling~\cite{RahulTED2013} and variation impacts~\cite{AvciIEDM2013, VinayNanoarch2011} provide more insights for design tradeoffs between energy efficiency and reliability. 

\begin{figure*}[ht!]
\centering
%\epsfig{file=figs/modeling.eps, angle=0, height=0.6\linewidth, clip=}
\epsfig{file=figs/modeling-correction.eps, angle=0, width=0.8\linewidth, clip=}
\caption{\label{fig:modeling} Device-to-architecture abstraction model for Steep Slope Processors}
\end{figure*}

%Critical path modeling
An architecture-level abstraction from the aforementioned circuit design can be obtained in different ways, depending on the nature of the processor configuration. 
The critical path delay of a CMOS-based in-order core is obtained by calibrating the delay of a series of cascaded FO4 inverters to form a ring oscillator with the frequency of an existing Intel Atom processor configuration. The total core power is obtained by multiplying the individual transistor power by the total number of transistors in the processor. The TFET processor critical path delay and power at different supply voltages are obtained by scaling the corresponding FinFET core parameters at that particular voltage. Further details regarding this modeling technique are described in~\cite{codes12}. 

On the other hand, due to the diversity in critical paths in out-of-order cores, a simple ring-oscillator model may not be sufficiently accurate.
Hence, we carry out power and timing evaluations of existing processor designs such as Intel IvyBridge using an architectural simulator, namely Sniper~\cite{Sniper} which is integrated with McPAT~\cite{mcpat}, a power and timing estimation tool. We instrument McPAT to output the critical path delay and power for a 22nm FinFET processor design and obtain the corresponding TFET core numbers by scaling the device parameters as in the previous case.
In addition, wire delay and power form an important constituent of the overall processor delay and power. We instrument McPAT to obtain the power and delay of the most significant microarchitectural components and add a model for wire power and delay for both FinFET and TFET technologies.
When added to the existing processor model, we observe a slight increase in the crossover frequency ($f_{cw}$) in comparison to the crossover frequency in the absence of wire effects ($f_{cno-w}$).
This is on account of the fact that the wire delay remains roughly constant, irrespective of the transistor technology.
This complete methodology is illustrated in Figure~\ref{fig:modeling}. 

%With critical path abstraction and TFET stand-cell library design from circuit-level simulation, architecture-level design for TFET technology has been further investigated...

